Computer Organization and Architecture

• Syllabus
• University Question - APRIL/MAY 2010

COA - University Question - APRIL/MAY 2010

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2010.
Fourth Semester
Computer Science and Engineering
CS2253 - COMPUTER ORGANIZATION AND ARCHITECTURE
(Common to Information Technology)
(Regulation 2008)

Time: Three hours                                                                                                Maximum:100 marks

Answer ALL Questions.
PART A- (10 X 2= 20 marks)

1. Distinguish between autoincrement and autodecrement addressing mode.
2. Compare RISC with CISC architecture.
3. Under what situations the micro program counter is not incremented after a new instruction is fetched from micro program memory?
4. What are the relative merits of horizontal and vertical micro instruction format?
5. What is pipelining and what are the advantages of pipelining?
6. List the key aspects in gaining the performance in pipelined systems.
7. How many memory chips are needed to construct 2M x 16 memory system using 512K x 8 static memory chips?
8. What is virtual memory and what are the benefits of virtual memory?
9. What is meant by bus arbitration?
10. Name and give the purpose of widely used bus standard.

PART B- (5 X 16 = 80 Marks)

11. (a) (i) Describe the role of system software to improve the performance of a computer. (8 Marks)
(ii) Design a 4- bit adder/ subtracter circuit using full adders and explain its function. (8 Marks)
(Or)
(b) (i) What are the special registers in a typical computer? Explain their purposes in detail. (8 Marks)
(ii) Design a 4- bit fast adder and explain its function in detail. (8 Marks)

12. (a) (i) Draw and explain the block diagram of a complete processor. (6 Marks)
(ii) Briefly describe the design of a hardwired control unit. (10 Marks)
(Or)
(b) (i) Explain the basic organization of a microprogrammed control unit and the generation of control signals using microprogram. (12 Marks)
(ii) What are the advantages and disadvantages of hardwired and microprogrammed control? (4 Marks)

13. (a) (i) Describe the role of cache memory in pipelined system. (8 Marks)
(ii) Discuss the influence of pipelining on instruction set design. (8 Marks)
(Or)
(b) What is instruction hazard? Explain the methods for dealing with the instruction hazards. (16 Marks)

14. (a) (i) What are the different secondary storage devices? Elaborate on any one of the devices. (8 Marks)
(ii) Explain how the virtual address is converted into real address in a paged virtual memory system. (8 Marks)
(Or)
(b) (i) Explain approaches for addressing multiple- module memory systems with suitable diagrams. (6 Marks)
(ii) Briefly describe magnetic disk principles and also the organization and accessing of data on a disk. (10 Marks)

15. (a) (i) Describe the hardware mechanism for handling multiple interrupt requests. (8 Marks)
(ii) What are handshaking signals? Explain the handshake control of data transfer during input and output operation. (8 Marks)
(Or)
(b) (i) What are the needs for input- output interface? Explain the functions of a typical 8- bit parallel interface in detail. (10 Marks)
(ii) Describe the USB architecture with the help of a neat diagram. (6 Marks)

CS 2253 - Computer Organization and Architecture - Syllabus

CS 2253 COMPUTER ORGANIZATION AND ARCHITECTURE

(Common to CSE & IT)

 L T P C

3 0 0 3

UNIT I           BASIC STRUCTURE OF COMPUTERS 9

Functional units – Basic operational concepts – Bus structures – Performance and metrics – Instructions and instruction sequencing – Hardware – Software Interface – Instruction set architecture – Addressing modes – RISC – CISC. ALU design – Fixed point and floating point operations.

UNIT II          BASIC PROCESSING UNIT        9

Fundamental concepts – Execution of a complete instruction – Multiple bus organization

– Hardwired control – Micro programmed control – Nano programming.

UNIT III        PIPELINING            9

Basic concepts – Data hazards – Instruction hazards – Influence on instruction sets –

Data path and control considerations – Performance considerations – Exception

handling.

UNIT IV        MEMORY SYSTEM          9

Basic concepts – Semiconductor RAM – ROM – Speed – Size and cost – Cache

memories – Improving cache performance – Virtual memory – Memory management

requirements – Associative memories – Secondary storage devices.

UNIT V          I/O ORGANIZATION         9

Accessing I/O devices – Programmed Input/Output -Interrupts – Direct Memory Access

– Buses – Interface circuits – Standard I/O Interfaces (PCI, SCSI, USB), I/O devices and

processors.

TOTAL: 45 PERIODS

TEXT BOOK:

1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer Organization”, Fifth

Edition, Tata McGraw Hill, 2002.

REFERENCES:

1. David A. Patterson and John L. Hennessy, “Computer Organization and Design: The

Hardware/Software interface”, Third Edition, Elsevier, 2005.

2. William Stallings, “Computer Organization and Architecture – Designing for

Performance”, Sixth Edition, Pearson Education, 2003.

3. John P. Hayes, “Computer Architecture and Organization”, Third Edition, Tata

McGraw Hill, 1998.

4. V.P. Heuring, H.F. Jordan, “Computer Systems Design and Architecture”, Second

Edition, Pearson Education, 2004.